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SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) product specification supersedes data of 2000 apr 03 2000 sep 22 integrated circuits
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2 2000 sep 22 853-2219 24638 description the SC28L91 is a new member of the impact family of serial communications controllers. it is a single channel uart operating at 3.3 and 5.0 volts vcc, 8 or 16 byte fifos and is quite compatible with software of the sc28l92 and previous uarts offered by philips. it is a new part that is similar to our previous one channel part but is vastly improved. the improvements being: 16 character receiver, 16 character transmit fifos, watch dog timer for the receiver, mode register 0 is added, extended baud rate, over all faster bus and data speeds, programmable receiver and transmitter interrupts and versatile i/o structure. (the previous one channel part, scc2691, is not being discontinued.) pin programming will allow the device to operate with either the motorola or intel bus interface. bit 3 of the mr0 register allows the device to operate in an 8-byte fifo mode if strict compliance with an 8-byte fifo structure is required. the philips semiconductors SC28L91 universal asynchronous receiver/transmitter (uart) is a single-chip cmos-lsi communications device that provides a full-duplex asynchronous receiver/transmitter channel in a single package. it interfaces directly with microprocessors and may be used in a polled or interrupt driven system with modem and dma interface. the operating mode and data format of the channel can be programmed independently. additionally, the receiver and transmitter can select its operating speed as one of 28 fixed baud rates; a 16x clock derived from a programmable counter/timer, or an external 1x or 16x clock. the baud rate generator and counter/timer can operate directly from a crystal or from external clock inputs. the ability to independently program the operating speed of the receiver and transmitter make the uart particularly attractive for dual-speed channel applications such as clustered terminal systems. the receiver and transmitter is buffered by 8 or 16 character fifos to minimize the potential of receiver overrun, transmitter underrun and to reduce interrupt overhead in interrupt driven systems. in addition, a flow control capability is provided via rts/cts signaling to disable a remote transmitter when the receiver buffer is full. dma interface is and other general purpose signals are provided on the SC28L91 via a multipurpose 7-bit input port and a multipurpose 8-bit output port. these can be used as general-purpose ports or can be assigned specific functions (such as clock inputs or status/interrupt outputs, fifo conditions) under program control. the SC28L91 is available in two package versions: a 44-pin plcc and 44-pin plastic quad flat pack (pqfp). features ? member of impact family: 3.3 to 5.0 volt , 40 c to +85 c and 68k for 80xxx bus interface for all devices. ? a full-duplex independent asynchronous receiver/transmitter ? 16 character fifos for each receiver and transmitter ? pin programming selects 68k or 80xxx-bus interface ? programmable data format 5 to 8 data bits plus parity odd, even, no parity or force parity 1, 1.5 or 2 stop bits programmable in 1/16-bit increments ? 16-bit programmable counter/timer ? programmable baud rate for each receiver and transmitter selectable from: 28 fixed rates: 50 to 230.4 k baud other baud rates to 1 mhz at 16x programmable user-defined rates derived from a programmable counter/timer external 1x or 16x clock ? parity, framing, and overrun error detection ? false start bit detection ? line break detection and generation ? programmable channel mode normal (full-duplex) automatic echo local loop back remote loop back multi-drop mode (also called `wake-up' or `9-bit') ? multi-function 7-bit input port (includes iackn) can serve as clock or control inputs change of state detection on four inputs inputs have typically >100k pull-up resistors change of state detectors for modem control ? multi-function 8-bit output port individual bit set/reset capability outputs can be programmed to be status/interrupt signals fifo status for dma interface ? versatile interrupt system single interrupt output with eight maskable interrupting conditions output port can be configured to provide a total of up to six separate interrupt outputs that may be wire ored. each fifo can be programmed for four different interrupt levels watch dog timer for the receiver ? maximum data transfer rates: 1x 1mb/sec, 16x 1mb/sec ? automatic wake-up mode for multi-drop applications ? start-end break interrupt/status with mid-character break detect. ? on-chip crystal oscillator ? power down mode ? receiver time-out mode ? single +3.3v or +5v power supply
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 3 ordering inormation industrial v cc = +3.3 10%, +5v 10% description t amb = 40 to +85 c drawing number 44-pin plastic leaded chip carrier (plcc) SC28L91a1a sot187-2 44-pin plastic quad flat pack (pqfp) SC28L91a1b sot307-2
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 4 pin configuration diagram 80xxx pin configuration pin function 1a3 2 ip0 3 wrn 4 rdn 5v cc 6 no connection 7 op1 8 op3 9 op5 10 op7 11 i/m 12 d1 13 d3 14 d5 15 d7 pin function 16 gnd 17 gnd 18 intrn 19 d6 20 d4 21 d2 22 d0 23 nc 24 op6 25 op4 26 op2 27 op0 28 txda 29 rxda 30 x1/clk pin function 31 x2 32 reset 33 cen 34 ip2 35 ip6 36 ip5 37 ip4 38 v cc 39 v cc 40 a0 41 ip3 42 a1 43 ip1 44 a2 pqfp 44 34 1 11 33 23 12 22 sd00698 1 39 17 28 40 29 18 7 plcc 6 sd00699 pin function 1nc 2a0 3 ip3 4a1 5 ip1 6a2 7a3 8 ip0 9 wrn 10 rdn 11 v cc 12 i/m 13 no connection 14 op1 15 op3 pin function 16 op5 17 op7 18 d1 19 d3 20 d5 21 d7 22 v ss 23 nc 24 intrn 25 d6 26 d4 27 d2 28 d0 29 op6 30 op4 pin function 31 op2 32 op0 33 txda 34 nc 35 rxda 36 x1/clk 37 x2 38 reset 39 cen 40 ip2 41 ip6 42 ip5 43 ip4 44 v cc note: pins marked ano connectiono must not be connected.
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 5 pin configuration diagram 68xxx pin configuration pin function 1a3 2 ip0 3 r/wn 4 dackn 5v cc 6 no connection 7 op1 8 op3 9 op5 10 op7 11 i/m 12 d1 13 d3 14 d5 15 d7 pin function 16 gnd 17 gnd 18 intrn 19 d6 20 d4 21 d2 22 d0 23 nc 24 op6 25 op4 26 op2 27 op0 28 txda 29 rxda 30 x1/clk pin function 31 x2 32 resetn 33 cen 34 ip2 35 iackn 36 ip5 37 ip4 38 v cc 39 v cc 40 a0 41 ip3 42 a1 43 ip1 44 a2 pqfp 44 34 1 11 33 23 12 22 sd00700 1 39 17 28 40 29 18 7 plcc 6 sd00701 pin function 1nc 2a0 3 ip3 4a1 5 ip1 6a2 7a3 8 ip0 9 r/wn 10 dackn 11 v cc 12 i/m 13 no connection 14 op1 15 op3 pin function 16 op5 17 op7 18 d1 19 d3 20 d5 21 d7 22 v ss 23 nc 24 intrn 25 d6 26 d4 27 d2 28 d0 29 op6 30 op4 pin function 31 op2 32 op0 33 txda 34 nc 35 rxda 36 x1/clk 37 x2 38 resetn 39 cen 40 ip2 41 iackn 42 ip5 43 ip4 44 v cc note: pins marked ano connectiono must not be connected.
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 6 8 d0d7 rdn wrn cen a0a3 reset intrn x1/clk x2 4 bus buffer operation control address decode r/w control interrupt control imr isr timing baud rate generator clock selectors counter/ timer xtal osc csr acr ctl data channel 16 byte transmit fifo transmit shift register 16 byte receive fifo mra0, 1, 2 cra sra input port change of state detectors (4) output port function select logic opcr txda rxda ip0-ip6 op0-op7 v cc v ss control timing internal databus ipcr acr opr ctu 8 7 watch dog timer receive shift register sd00702 gp figure 1. block diagram (80xxx mode)
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 7 8 d0d7 r/wn cen a0a3 resetn intrn x1/clk x2 4 bus buffer operation control address decode r/w control interrupt control imr isr timing baud rate generator clock selectors counter/ timer xtal osc csr acr ctl data channel 16 byte transmit fifo transmit shift register 16 byte receive fifo mra0, 1, 2 cra sra input port change of state detectors (4) output port function select logic opcr txda rxda ip0-ip5 op0-op7 v cc v ss control timing internal databus ipcr acr opr ctu 8 6 watch dog timer receive shift register sd00703 ivr dackn iackn figure 2. block diagram (68xxx mode)
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 8 pin configuration for 80xxx bus interface (intel ? ) symbol pin type name and function i/m i bus configuration: when high or not connected configures the bus interface to the conditions shown in this table. d0d7 i/o data bus: bi-directional 3-state data bus used to transfer commands, data and status between the uart and the cpu. d0 is the least significant bit. cen i chip enable: active-low input signal. when low, data transfers between the cpu and the uart are enabled on d0d7 as controlled by the wrn, rdn and a0a3 inputs. when high, places the d0d7 lines in the 3-state condi- tion. wrn i write strobe: when low and cen is also low, the contents of the data bus is loaded into the addressed register. the transfer occurs on the rising edge of the signal. rdn i read strobe: when low and cen is also low, causes the contents of the addressed register to be presented on the data bus. the read cycle begins on the falling edge of rdn. a0a3 i address inputs: select the uart internal registers and ports for read/write operations. reset i reset: a high level clears internal registers (sr, imr, isr, opr, opcr), puts op0op7 in the high state, stops the counter/timer, and puts the channel in the inactive state, with the txd outputs in the mark (high) state. sets mr point- er to mr1. see figure 4 intrn o interrupt request: active-low, open-drain, output which signals the cpu that one or more of the eight maskable in- terrupting conditions are true. this pin requires a pull-up device. x1/clk i crystal 1: crystal or external clock input. a crystal or clock of the specified limits must be supplied at all times. when a crystal is used, a capacitor must be connected from this pin to ground (see figure 11). x2 o crystal 2: connection for other side of the crystal. when a crystal is used, a capacitor must be connected from this pin to ground (see figure 11). if x1/clk is driven from an external source, this pin must be left open. rxd i receiver serial data input: the least significant bit is received first. amarko is high; aspaceo is low. txd o transmitter serial data output: the least significant bit is transmitted first. this output is held in the amarko condition when the transmitter is disabled, idle or operating in local loop back mode. amarko is high; aspaceo is low. op0 o output 0: general-purpose output or request to send (rtsn, active-low). can be deactivated automatically on re- ceive or transmit. op1 o output 1: general-purpose output. op2 o output 2: general-purpose output, or transmitter 1x or 16x clock output, or receiver 1x clock output. op3 o output 3: general-purpose output. op4 o output 4: general-purpose output or open-drain, active-low, rx interrupt isr[1] output. dma control op5 o output 5: general-purpose output op6 o output 6: general-purpose output or open-drain, active-low, tx interrupt isr[0] output. dma control op7 o output 7: general-purpose output. ip0 i input 0: general-purpose input or clear to send active-low input (ctsn). has change of state dector. ip1 i input 1: general-purpose input. has change of state dector. ip2 i i nput 2: general-purpose input or counter/timer external clock input. has change of state dector. ip3 i input 3: general-purpose input or transmitter external clock input (txc). when the external clock is used by the trans- mitter, the transmitted data is clocked on the falling edge of the clock. has change of state dector. ip4 i input 4: general-purpose input or receiver external clock input (rxc). when the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. ip5 i input 5: general-purpose input ip6 i input 6: general-purpose input v cc pwr power supply: +3.3 or +5v supply input 10% gnd pwr ground
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 9 pin configuration for 68xxx bus interface (motorola ? ) symbol pin type name and function i/m i bus configuration : when low configures the bus interface to the conditions shown in this table. d0d7 i/o data bus : bi-directional 3-state data bus used to transfer commands, data and status between the uart and the cpu. d0 is the least significant bit. cen i chip enable : active-low input signal. when low, data transfers between the cpu and the uart are enabled on d0d7 as controlled by the r/wn and a0a3 inputs. when high, places the d0d7 lines in the 3-state condition. r/wn i read/write : input signal. when cen is low r/wn high input indicates a read cycle; when low indicates a write cycle. iackn i interrupt acknowledge : active low input indicating an interrupt acknowledge cycle. usually asserted by the cpu in response to an interrupt request. when asserted places the interrupt vector on the bus and asserts dackn. dackn o data transfer acknowledge : a3-state active-low output asserted in a write, read, or interrupt acknowledge cycle to indicate proper transfer of data between the cpu and the uart. a0a3 i address inputs : select the uart internal registers and ports for read/write operations. resetn i reset : a low level clears internal registers (sra, srb, imr, isr, opr, opcr), puts op0op7 in the high state, stops the counter/timer, and puts the channel in the inactive state, with the txd outputs in the mark (high) state. sets mr pointer to mr1. see figure 4 intrn o interrupt request : active-low, open-drain, output which signals the cpu that one or more of the eight maskable interrupting conditions are true. this pin requires a pullup. x1/clk i crystal 1 : crystal or external clock input. a crystal or clock of the specified limits must be supplied at all times. when a crystal is used, a capacitor must be connected from this pin to ground (see figure 11). x2 o crystal 2 : connection for other side of the crystal. when a crystal is used, a capacitor must be connected from this pin to ground (see figure 11). if x1/clk is driven from an external source, this pin must be left open. rxd i receiver serial data input : the least significant bit is received first. amarko is high, aspaceo is low. txd o transmitter serial data output : the least significant bit is transmitted first. this output is held in the `mark' condition when the transmitter is disabled, idle, or when operating in local loop back mode. `mark' is high; `space' is low. op0 o output 0 : general purpose output or request to send (rtsan, active-low). can be deactivated automatically on receive or transmit. op1 o output 1 : general-purpose output. op2 o output 2 : general purpose output or transmitter 1x or 16x clock output, or receiver 1x clock output. op3 o output 3 : general purpose output. op4 o output 4 : general purpose output or open-drain, active-low, rxa interrupt isr [1] output. dma control op5 o output 5 : general-purpose output. op6 o output 6 : general purpose output or open-drain, active-low, txa interrupt isr[0] output. dma control op7 o output 7 : general-purpose output. ip0 i input 0 : general purpose input or clear to send active-low input (ctsan). has change of state dector. ip1 i input 1 : general purpose input. has change of state dector. ip2 i input 2 : general-purpose input or counter/timer external clock input. has change of state dector. ip3 i input 3 : general purpose input or transmitter external clock input (txc). when the external clock is used by the trans- mitter, the transmitted data is clocked on the falling edge of the clock. has change of state dector. ip4 i input 4 : general purpose input or receiver external clock input (rxc). when the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. ip5 i input 5 : general purpose input. v cc pwr power supply : +3.3 or +5v supply input 10% gnd pwr ground
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 10 absolute maximum ratings 1 symbol parameter rating unit t amb operating ambient temperature range 2 note 4 c t stg storage temperature range 65 to +150 c v cc voltage from v cc to gnd 3 0.5 to +7.0 v v s voltage from any pin to gnd 3 0.5 to v cc +0.5 v p d package power dissipation (plcc44) 2.4 w p d package power dissipation (pqfp44) 1.78 w derating factor above 25 c (plcc44) 19 mw/ c derating factor above 25 c (pqfp44) 14 mw/ c notes: 1. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operation section of this speci fication is not implied. 2. for operating at elevated temperatures, the device must be derated based on +150 c maximum junction temperature. 3. this product includes circuitry specifically designed for the protection of its internal devices from damaging effects of exc essive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rate d maxima. 4. parameters are valid over specified temperature and voltage range. dc electrical characteristics 1, 2, 3 v cc = 5v 10%, t amb = 40 c to +85 c, unless otherwise specified. symbol parameter conditions min typ max unit v il input low voltage 0.8 v v ih input high voltage (except x1/clk) 2.4 1.5 v v ih input high voltage (x1/clk) 0.8*v cc 2.4 v v ol output low voltage i ol = 2.4ma 0.2 0.4 v v oh output high voltage (except od outputs) 4 i oh = -400 m a v cc -0.5 v i ix1pd x1/clk input current - power down v in = 0 to v cc 0.5 0.05 0.5 m a i ilx1 x1/clk input low current - operating v in = 0 130 0 m a i ihx1 x1/clk input high current - operating v in = v cc 0 130 m a input leakage current: i i all except input port pins v in = 0 to v cc 0.5 0.05 +0.5 m a input port pins 5 v in = 0 to v cc 8 0.05 +0.5 m a i ozh output off current high, 3-state data bus v in = v cc 0.5 m a i ozl output off current low, 3-state data bus v in = 0v 0.5 m a i odl open-drain output low current in off-state v in = 0 0.5 m a i odh open-drain output high current in off-state v in = v cc 0.5 m a power supply current 6 i cc operating mode cmos input levels 7 25 ma power down mode cmos input levels 1 5 a notes: 1. parameters are valid over specified temperature and voltage range. 2. all voltage measurements are referenced to ground (gnd). for testing, all inputs swing between 0.4 v and 3.0 v with a transit ion time of 5ns maximum. for x1/clk, this swing is between 0.4 v and 0.8*v cc . all time measurements are referenced at input voltages of 0.8v and 2.0v and output voltages of 0.8 v and 2.0 v, as appropriate. 3. typical values are at +25 c, typical supply voltages, and typical processing parameters. 4. test conditions for outputs: c l = 125 pf, except open drain outputs. test conditions for open drain outputs: c l = 125 pf, constant current source = 2.6 ma. 5. input port pins have active pull-up transistors that will source a typical 2 m a from v cc when the input pins are at v ss . input port pins at v cc source 0.0 m a. 6. all outputs are disconnected. inputs are switching between cmos levels of v cc -0.2 v and v ss + 0.2 v.
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 11 dc electrical characteristics 1, 2, 3 v cc = 3.3v 10%, t amb = 40 c to +85 c, unless otherwise specified. symbol parameter conditions min typ max unit v il input low voltage 0.65 0.2*v cc v v ih input high voltage 0.8*v cc 1.7 v v ol output low voltage i ol = 2.4ma 0.2 0.4 v v oh output high voltage (except od outputs) 4 i oh = 400 m a v cc 0.5 v cc 0.2 v i ix1pd x1/clk input current - power down v in = 0 to v cc 0.5 0.05 +0.5 m a i ilx1 x1/clk input low current - operating v in = 0 80 0 m a i ihx1 x1/clk input high current - operating v in = v cc 0 80 m a input leakage current: i i all except input port pins v in = 0 to v cc 0.5 0.05 +0.5 m a input port pins 5 v in = 0 to v cc 8 0.5 +0.5 m a i ozh output off current high, 3-state data bus v in = v cc 0.5 m a i ozl output off current low, 3-state data bus v in = 0v 0.5 m a i odl open-drain output low current in off-state v in = 0 0.5 m a i odh open-drain output high current in off-state v in = v cc 0.5 m a power supply current 6 i cc operating mode cmos input levels 5 ma power down mode cmos input levels 1 5.0 a notes: 1. parameters are valid over specified temperature and voltage range. 2. all voltage measurements are referenced to ground (gnd). for testing, all inputs swing between 0.4 v and 3.0 v with a transit ion time of 5ns maximum. for x1/clk, this swing is between 0.4 v and 0.8*v cc . all time measurements are referenced at input voltages of 0.8 v and 2.0v and output voltages of 0.8 v and 2.0 v, as appropriate. 3. typical values are at +25 c, typical supply voltages, and typical processing parameters. 4. test conditions for outputs: c l = 125 pf, except open drain outputs. test conditions for open drain outputs: c l = 125 pf, constant current source = 2.6 ma. 5. input port pins have active pull-up transistors that will source a typical 2 m a from v cc when the input pins are at v ss . input port pins at v cc source 0.0 m a. 6. all outputs are disconnected. inputs are switching between cmos levels of v cc 0.2 v and v ss +0.2 v.
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 12 ac characteristics (5 volt) 1, 2, 3, 4 v cc = 5.0v 10%, t amb = 40 c to +85 c, unless otherwise specified. symbol parameter min typ max unit reset timing (see figure 4) t res reset pulse width 100 18 ns bus timing 5 (see figure 5) t *as a0a3 setup time to rdn, wrn low 10 6 ns t *ah a0a3 hold time from rdn, wrn low 20 12 ns t *cs cen setup time to rdn, wrn low 0 ns t *ch cen hold time from rdn. wrn low 0 ns t *rw wrn, rdn pulse width (low time) 15 8 ns t *dd data valid after rdn low (125pf load. see figure 3 for smaller loads.) 40 55 ns t *da rdn low to data bus active 6 0 ns t *df data bus floating after rdn or cen high 20 ns t *di rdn or cen high to data bus invalid 7 0 ns t *ds data bus setup time before wrn or cen high (write cycle) 25 17 ns t *dh data hold time after wrn high 0 12 ns t *rwd high time between read and/or write cycles 5, 7 15 10 ns port timing 5 (see figure 9) t *ps port in setup time before rdn low (read ip ports cycle) 0 20 ns t *ph port in hold time after rdn high 0 20 ns t *pd op port valid after wrn or cen high (opr write cycle) 40 60 ns interrupt timing (see figure 10) t *ir intrn (or op3op7 when used as interrupts) negated from: read rxfifo (rxrdy/ffull interrupt) 40 60 ns write txfifo (txrdy interrupt) 40 60 ns reset command (delta break change interrupt) 40 60 ns stop c/t command (counter/timer interrupt 40 60 ns read ipcr (delta input port change interrupt) 40 60 ns write imr (clear of change interrupt mask bit(s)) 40 60 ns clock timing (see figure 11) t *clk x1/clk high or low time 30 20 ns f *clk x1/clk frequency 8 (for higher speeds contact factory) 0.1 3.686 8.0 mhz f *ctc c/t clk (ip2) high or low time (c/t external clock input) 30 10 ns f *ctc c/t clk (ip2) frequency 8 (for higher speeds contact factory) 0 8.0 mhz t *rx rxc high or low time (16x) 30 10 ns f *rx rxc frequency (16x)(for higher speeds contact factory) 0 16 mhz rxc frequency (1x) 8, 9 0 1 mhz t *tx txc high or low time (16x) 30 10 ns f *tx txc frequency (16x) (for higher speeds contact factory) 16 mhz txc frequency (1x) 8, 9 0 1 mhz transmitter timing, external clock (see figure 12) t *txd txd output delay from txc low (txc input pin) 40 60 ns t *tcs output delay from txc output pin low to txd data output 6 30 ns
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 13 unit max typ min parameter symbol receiver timing, external clock (see figure 13) t *rxs rxd data setup time to rxc high 50 40 ns t *rxh rxd data hold time from rxc high 50 40 ns 68000 or motorola bus timing (see figures 6, 7, 8) 10 t dcr dackn low (read cycle) from x1 high 10 15 20 ns t dcw dackn low (write cycle) from x1 high 15 20 ns t dat dackn high impedance from cen or iackn high 8 10 ns t csc cen or iackn setup time to x1 high for minimum dackn cycle 10 8 ns notes: 1. parameters are valid over specified temperature and voltage range. 2. all voltage measurements are referenced to ground (gnd). for testing, all inputs swing between 0.4 v and 3.0 v with a transit ion time of 5 ns maximum. for x1/clk this swing is between 0.4 v and 0.8*v cc . all time measurements are referenced at input voltages of 0.8 v and 2.0 v and output voltages of 0.8 v and 2.0 v, as appropriate. 3. test conditions for outputs: cl = 125 pf, except open drain outputs. test conditions for open drain outputs: c l = 125 pf, constant current source = 2.6 ma. 4. typical values are the average values at +25 c and 5 v. 5. timing is illustrated and referenced to the wrn and rdn inputs. also, cen may be the astrobingo input. cen and rdn (also cen and wrn) are ored internally. the signal asserted last initiates the cycle and the signal negated first terminates the cycle. 6. guaranteed by characterization of sample units. 7. if cen is used as the astrobingo input, the parameter defines the minimum high times between one cen and the next. the rdn si gnal must be negated for t rwd to guarantee that any status register changes are valid. 8. minimum frequencies are not tested but are guaranteed by design. 9. clocks for 1x mode should maintain a 60/40 duty cycle or better. 10. minimum dackn time is t dcr = t dsc + t dcr + two positive edges of the x1 clock. for faster bus cycles, the 80xxx bus timing may be used while in the 68xxx mode. it is not necessary to wait for dackn to insure the proper operation of the sc28c91. in all cases the data will be written to the SC28L91 on the falling edge of dackn or the rise of cen. the fall of cen initializes the bus cycle. the rise of cen ends the bus cycle. dackn low or cen high completes the write cycle. 0 20 40 60 80 100 120 140 160 180 200 220 240 60 55 50 45 40 35 30 25 20 15 10 5 0 v cc = 3.3v @ +25 c 5.0v @ +25 c pf t dd (ns) 125 pf 30 pf 230 pf sd00684 12 pf 100 pf notes: bus cycle times: (80xxx mode): t dd + t rwd = 70 ns @ 5v, 40 ns @ 3.3 v + rise and fall time of control signals (68xxx mode) = t csc + t dat + 1 cycle of the x1 clock @ 5 v + rise and fall time of control signals figure 3. port timing vs. capacitive loading at typical conditions
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 14 ac characteristics (3.3 volt) 1, 2, 3, 4 v cc = 3.3v 10%, t amb = 40 c to +85 c, unless otherwise specified. symbol parameter min typ max unit reset timing (see figure 4) t res reset pulse width 100 20 ns bus timing 5 (see figure 5) t *as a0a3 setup time to rdn, wrn low 10 6 ns t *ah a0a3 hold time from rdn, wrn low 25 16 ns t *cs cen setup time to rdn, wrn low 0 ns t *ch cen hold time from rdn. wrn low 0 ns t *rw wrn, rdn pulse width (low time) 20 10 ns t *dd data valid after rdn low (125pf load. see figure 3 for smaller loads.) 46 75 ns t *da rdn low to data bus active 6 0 ns t *df data bus floating after rdn or cen high 15 20 ns t *di rdn or cen high to data bus invalid 7 0 ns t *ds data bus setup time before wrn or cen high (write cycle) 25 20 ns t *dh data hold time after wrn high 0 15 ns t *rwd high time between read and/or write cycles 5, 7 20 10 ns port timing 5 (see figure 9) t *ps port in setup time before rdn low (read ip ports cycle) 0 20 ns t *ph port in hold time after rdn high 0 20 ns t *pd op port valid after wrn or cen high (opr write cycle) 50 70 ns interrupt timing (see figure 10) t *ir intrn (or op3op7 when used as interrupts) negated from: read rxfifo (rxrdy/ffull interrupt) 40 60 ns write txfifo (txrdy interrupt) 40 60 ns reset command (delta break change interrupt) 40 60 ns stop c/t command (counter/timer interrupt) 40 60 ns read ipcr (delta input port change interrupt) 40 60 ns write imr (clear of change interrupt mask bit(s)) 40 60 ns clock timing (see figure 11) t *clk x1/clk high or low time 30 25 ns f *clk x1/clk frequency 8 (for higher speeds contact factory) 0.1 3.686 8 mhz f *ctc c/t clk (ip2) high or low time (c/t external clock input) 30 15 ns f *ctc c/t clk (ip2) frequency 8 (for higher speeds contact factory) 0 8 mhz t *rx rxc high or low time (16x) 30 10 ns f *rx rxc frequency (16x) (for higher speeds contact factory) 0 16 mhz rxc frequency (1x) 8, 9 0 1 mhz t *tx txc high or low time (16x) 30 15 ns f *tx txc frequency (16x) (for higher speeds contact factory) 16 mhz txc frequency (1x) 8, 9 0 1 mhz transmitter timing, external clock (see figure 12) t *txd txd output delay from txc low (txc input pin) 40 60 ns t *tcs output delay from txc output pin low to txd data output 8 30 ns
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 15 unit max typ min parameter symbol receiver timing, external clock (see figure 13) t *rxs rxd data setup time to rxc high 50 10 ns t *rxh rxd data hold time from rxc high 50 10 ns 68000 or motorola bus timing (see figures 6, 7, 8) 10 t dcr dackn low (read cycle) from x1 high 10 18 25 ns t dcw dackn low (write cycle) from x1 high 18 25 ns t dat dackn high impedance from cen or iackn high 10 15 ns t csc cen or iackn setup time to x1 high for minimum dackn cycle 15 10 ns notes: 1. parameters are valid over specified temperature and voltage range. 2. all voltage measurements are referenced to ground (gnd). for testing, all inputs swing between 0.4 v and 3.0 v with a transit ion time of 5 ns maximum. for x1/clk this swing is between 0.4 v and 0.8*v cc . all time measurements are referenced at input voltages of 0.8 v and 2.0 v and output voltages of 0.8 v and 2.0 v, as appropriate. 3. test conditions for outputs: cl = 125 pf, except open drain outputs. test conditions for open drain outputs: c l = 125 pf, constant current source = 2.6 ma. 4. typical values are the average values at +25 c and 3.3 v. 5. timing is illustrated and referenced to the wrn and rdn inputs. also, cen may be the astrobingo input. cen and rdn (also cen and wrn) are ored internally. the signal asserted last initiates the cycle and the signal negated first terminates the cycle. 6. guaranteed by characterization of sample units. 7. if cen is used as the astrobingo input, the parameter defines the minimum high times between one cen and the next. the rdn si gnal must be negated for t rwd to guarantee that any status register changes are valid. 8. minimum frequencies are not tested but are guaranteed by design. 9. clocks for 1x mode should maintain a 60/40 duty cycle or better. 10. minimum dackn time is t dcr = t dsc + t dcr + two positive edges of the x1 clock. for faster bus cycles, the 80xxx bus timing may be used while in the 68xxx mode. it is not necessary to wait for dackn to insure the proper operation of the sc28c91. in all cases the data will be written to the SC28L91 on the falling edge of dackn or the rise of cen. the fall of cen initializes the bus cycle. the rise of cen ends the bus cycle. dackn low or cen high completes the write cycle.
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 16 block diagram the SC28L91 uart consists of the following seven major sections: data bus buffer, operation control, interrupt control, timing, rx and tx fifo buffers, input port and output port control. refer to the block diagram. data bus buffer the data bus buffer provides the interface between the external and internal data buses. it is controlled by the operation control block to allow read and write operations to take place between the controlling cpu and the uart. operation control the operation control logic receives operation commands from the cpu and generates appropriate signals to internal sections to control device operation. it contains address decoding and read and write circuits to permit communications with the microprocessor via the data bus. interrupt control a single active-low interrupt output (intrn) is provided which is activated upon the occurrence of any of eight internal events. associated with the interrupt system are the interrupt mask register (imr) and the interrupt status register (isr). the imr can be programmed to select only certain conditions to cause intrn to be asserted. the isr can be read by the cpu to determine all currently active interrupting conditions. outputs op3op7 can be programmed to provide discrete interrupt outputs for the transmitter, receiver, and counter/timer. programming the op3 to op7 pins as interrupts causes their output buffers to change to an open drain active low configuration. the op pins may be used for dma and modem control as well. (see output port notes). fifo configuration each receiver and transmitter has a 16 byte fifo. these fifos may be configured to operate at a fill capacity of either 8 or 16 bytes. this feature may be used if it is desired to operate the 28l91 in close compliance to 26c92 software. the 8-byte/16-byte mode is controlled by the mr0[3] bit. a 0 value for this bit sets the 8-bit mode ( the default); a 1 sets the 16-byte mode. the fifo fill interrupt level automatically follow the programming of the mr0[3] bit. see tables 3 and 4. 68xxx mode when the i/m pin is connected to v ss (ground), the operation of the SC28L91 switches to the bus interface compatible with the motorola bus interfaces. several of the pins change their function as follows: ? ip6 becomes iackn input ? rdn becomes dackn ? wrn becomes r/wn the interrupt vector is enabled and the interrupt vector will be placed on the data bus when iackn is asserted low. the interrupt vector register is located at address 0xc. the contents of this register are set to 0x0f on the application of resetn. the generation of dackn uses two positive edges of the x1 clock as the dackn delay from the falling edge of cen. if the cen is withdrawn before two edges of the x1 clock occur, the generation of dackn is terminated. systems not strictly requiring dackn may use the 68xxx mode with the bus timing of the 80xxx mode greatly decreasing the bus cycle time. timing circuits crystal clock the timing block consists of a crystal oscillator, a baud rate generator, a programmable 16-bit counter/timer, and four clock selectors. the crystal oscillator operates directly from a crystal connected across the x1/clk and x2 inputs. if an external clock of the appropriate frequency is available, it may be connected to x1/clk. the clock serves as the basic timing reference for the baud rate generator (brg), the counter/timer, and other internal circuits. a clock signal within the limits specified in the specifications section of this data sheet must always be supplied to the uart. if an external clock is used instead of a crystal, x1 should be driven using a configuration similar to the one in figure 11. x2 should be open or driving a nominal gate load. nominal crystal rate is 3.6864 mhz. rates up to 8 mhz may be used. brg the baud rate generator operates from the oscillator or external clock input and is capable of generating 28 commonly used data communications baud rates ranging from 50 to 38.4 k baud. programming bit 0 of mr0 to a a1o gives additional baud rates of 57.6 kb, 115.2 kb and 230.4 kb (500 khz with x1 at 8.0 mhz). these will be in the 16x mode. a 3.6864 mhz crystal or external clock must be used to get the standard baud rates. the clock outputs from the brg are at 16x the actual baud rate. the counter/timer can be used as a timer to produce a 16x clock for any other baud rate by counting down the crystal clock or an external clock. the four clock selectors allow the independent selection, for the receiver and transmitter, of any of these baud rates or external timing signal. counter/timer the counter timer is a 16-bit programmable divider that operates in one of three modes: counter, timer, and time out. in the timer mode it generates a square wave. in the counter mode it generates a time delay. in the time out mode it monitors the time between received characters. the c/t uses the numbers loaded into the counter/timer lower register (ctlr) and the counter/timer upper register (ctur) as its divisor. the counter/timer clock source and mode of operation (counter or timer) is selected by the auxiliary control register bits 6 to 4 (acr[6:4]). the output of the counter/timer may be used for a baud rate and/or may be output to the op pins for some external function that may be totally unrelated to data transmission. the counter/timer also sets the counter/timer ready bit in the interrupt status register (isr) when its output transitions from 1 to 0. a register read address (see table 1) is reserved to issue a start counter/timer command and a second register read address is reserved to issue a stop command. the value of d[7:0] is ignored. the start command always loads the contents of ctur, ctlr to the counting registers. the stop command always resets the isr[3] bit in the interrupt status register. timer mode in the timer mode a symmetrical square wave is generated whose half period is equal in time to division of the selected counter/timer clock frequency by the 16-bit number loaded in the ctlr ctur. thus, the frequency of the counter/timer output will be equal to the counter/timer clock frequency divided by twice the value of the ctur ctlr. while in the timer mode the isr bit 3 (isr[3]) will be set each time the counter/timer transitions from 1 to 0. (high to low)
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 17 this continues regardless of issuance of the stop counter command. isr[3] is reset by the stop counter command. note: reading of the ctu and ctl registers in the timer mode is not meaningful. when the c/t is used to generate a baud rate and the c/t is selected through the csr then the receiver and/or transmitter will be operating in the 16x mode. calculation for the number `n' to program the counter timer upper and lower registers is shown below. n c tclockrate 2 * 16 * baud rate often this division will result in a non-integer number; 26.3 for example. one can only program integer numbers to a digital divider. therefore 26 would be chosen. this gives a baud rate error of 0.3/26.3 which is 1.14%; well within the ability of the asynchronous mode of operation. counter mode in the counter mode the counter/timer counts the value of the ctlr ctur down to zero and then sets the isr[3] bit and sets the counter/timer output from 1 to 0. it then rolls over to 65,365 and continues counting with no further observable effect. reading the c/t in the counter mode outputs the present state of the c/t. if the c/t is not stopped, a read of the c/t may result in changing data on the data bus. timeout mode the timeout mode uses the received data stream to control the counter. the time-out mode forces the c/t into the timer mode. each time a received character is transferred from the shift register to the rxfifo, the counter is restarted. if a new character is not received before the counter reaches zero count, the counter ready bit is set, and an interrupt can be generated. this mode can be used to indicate when data has been left in the rx fifo for more than the programmed time limit. if the receiver has been programmed to interrupt the cpu when the receive fifo is full, and the message ends before the fifo is full, the cpu will not be interrupted for the remaining characters in the rxfifo. by programming the c/t such that it would time out in just over one character time, the above situation could be avoided. the processor would be interrupted any time the data stream had stopped for more than one character time. note: this is very similar to the watch dog timer of mr0. the difference is in the programmability of the delay timer and that this indicates that the data stream has stopped. the watchdog timer is more of an indicator that data is in the fifo is not enough to cause an interrupt. the watchdog is restarted by either a receiver load to the rxfifo or a system read from it. this mode is enabled by writing the appropriate command to the command register. writing an `0xan' to cr will invoke the timeout mode for that channel. writing a `cx' to cr will disable the timeout mode. the timeout mode disables the regular start/stop counter commands and puts the c/t into counter mode under the control of the received data stream. each time a received character is transferred from the shift register to the rxfifo, the c/t is stopped after one c/t clock, reloaded with the value in ctur and ctlr and then restarted on the next c/t clock. if the c/t is allowed to end the count before a new character has been received, the counter ready bit, isr[3], will be set. if imr [3] is set, this will generate an interrupt. since receiving a character restarts the c/t, the receipt of a character after the c/t has timed out will clear the counter ready bit, isr [3], and the interrupt. invoking the `set timeout mode on' command, crx = 0xan, will also clear the counter ready bit and stop the counter until the next character is received. the counter timer is controlled with six commands: start/stop c/t, read/write counter/timer lower register and read/write counter/timer upper register. these commands have slight differences depending on the mode of operation. please see the detail of the commands under the ctlr ctur register descriptions. time out mode caution when operating in the special time out mode it is possible to generate what appears to be a afalse interrupto, i.e. an interrupt without a cause. this may result when a time-out interrupt occurs and then, before the interrupt is serviced, another character is received, i.e., the data stream has started again. (the interrupt latency is longer than the pause in the data stream.) in this case, when a new character has been receiver, the counter/timer will be restarted by the receiver, thereby withdrawing its interrupt. if, at this time, the interrupt service begins for the previously seen interrupt, a read of the isr will show the acounter readyo bit not set. if nothing else is interrupting, this read of the isr will return a x'00 character. this action may present the appearance of a spurious interrupt. communications the communications channel of the SC28L91 comprises a full-duplex asynchronous receiver/transmitter (uart). the operating frequency for the receiver and transmitter can be selected independently from the baud rate generator, the counter/timer, or from an external input. the transmitter accepts parallel data from the cpu, converts it to a serial bit stream, inserts the appropriate start, stop, and optional parity bits and outputs a composite serial stream of data on the txd output pin. the receiver accepts serial data on the rxd pin, converts this serial input to parallel format, checks for start bit, stop bit, parity bit (if any), or break condition and sends an assembled character to the cpu via the receive fifo. three status bits (break received, framing and parity errors) are also fifoed with the data character. input port the inputs to this unlatched 7-bit (6-bit for 68xxx mode) port can be read by the cpu by performing a read operation at address 0xd. a high input results in a logic 1 while a low input results in a logic 0. d7 will always read as a logic 1. the pins of this port can also serve as auxiliary inputs to certain portions of the uart logic, modem and dma. four change-of-state detectors are provided which are associated with inputs ip3, ip2, ip1 and ip0. a high-to-low or low-to-high transition of these inputs, lasting longer than 2550 s, will set the corresponding bit in the input port change register. the bits are cleared when the register is read by the cpu. any change-of-state can also be programmed to generate an interrupt to the cpu. the input port change of state detection circuitry uses a 38.4 khz sampling clock derived from one of the baud rate generator taps. this results in a sampling period of slightly more than 25 s (this assumes that the clock input is 3.6864 mhz). the detection circuitry, in order to guarantee that a true change in level has occurred, requires two successive samples at the new logic level be observed. as a consequence, the minimum duration of the signal change is 25 s if the transition occurs acoincident with the first sample pulseo. the 50 s time refers to the situation in which the change-of-state is
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 18 ajust missedo and the first change-of-state is not detected until 25 s later. output port the output ports are controlled from six places: the opcr, opr, mr, command, sopr and ropr registers. the opcr register controls the source of the data for the output ports op2 through op7. the data source for output ports op0 and op1 is controlled by the mr and cr registers. when the opr is the source of the data for the output ports, the data at the ports is inverted from that in the opr register. the content of the opr register is controlled by the aset output port bits commando and the areset output bits commando. these commands are at e and f, respectively. when these commands are used, action takes place only at the bit locations where ones exist. for example, a one in bit location 5 of the data word used with the aset output port bitso command will result in opr[5] being set to one. the op5 would then be set to zero (v ss ). similarly, a one in bit position 5 of the data word associated with the areset output ports bitso command would set opr[5] to zero and, hence, the pin op5 to a one (v dd ). these pins along with the ip pins and their change of state detectors are often used for modem and dma control. operation transmitter the SC28L91 is conditioned to transmit data when the transmitter is enabled through the command register. the SC28L91 indicates to the cpu that it is ready to accept a character by setting the txrdy bit in the status register. this condition can be programmed to generate an interrupt request at op6 or op7 and intrn. when the transmitter is initially enabled the txrdy and txempt bits will be set in the status register. when a character is loaded to the transmit fifo the txempt bit will be reset. the txempt will not set until: 1) the transmit fifo is empty and the transmit shift register has finished transmitting the stop bit of the last character written to the transmit fifo, or 2) the transmitter is disabled and then re-enabled. the txrdy bit is set whenever the transmitter is enabled and the txfifo is not full. data is transferred from the holding register to transmit shift register when it is idle or has completed transmission of the previous character. characters cannot be loaded into the txfifo while the transmitter is disabled. the transmitter converts the parallel data from the cpu to a serial bit stream on the txd output pin. it automatically sends a start bit followed by the programmed number of data bits, an optional parity bit, and the programmed number of stop bits. the least significant bit is sent first. following the transmission of the stop bits, if a new character is not available in the txfifo, the txd output remains high and the txemt bit in the status register (sr) will be set to 1. transmission resumes and the txemt bit is cleared when the cpu loads a new character into the txfifo. if the transmitter is disabled it continues operating until the character currently being transmitted and any characters in the txfifo, including parity and stop bits, have been transmitted. new data cannot be loaded to the txfifo when the transmitter is disabled. when the transmitter is reset it stops sending data immediately. the transmitter can be forced to send a break (a continuous low condition) by issuing a start break command via the cr register. the break is terminated by a stop break command or a transmitter reset. if cts option is enabled (mr2[4] = 1), the cts input at ip0 or ip1 must be low in order for the character to be transmitted. the transmitter will check the state of the cts input at the beginning of the character transmitted. if it is found to be high, the transmitter will delay the transmission of any following characters until the cts has returned to the low state. cts going high during the serialization of a character will not affect that character. the transmitter can also control the rtsn outputs, op0 or op1 via mr2[5]. when this mode of operation is set, the meaning of the op0 or op1 signals will usually be `end of message'. see description of the mr2[5] bit for more detail. this feature may be used to automatically aturn aroundo a transceiver in simplex systems. receiver the SC28L91 is conditioned to receive data when enabled through the command register. the receiver looks for a high-to-low (mark-to-space) transition of the start bit on the rxd input pin. if a transition is detected, the state of the rxd pin is sampled the 16x clock for 71/2 clocks (16x clock mode) or at the next rising edge of the bit time clock (1x clock mode). if rxd is sampled high, the start bit is invalid and the search for a valid start bit begins again. if rxd is still low, a valid start bit is assumed and the receiver continues to sample the input at one-bit time intervals at the theoretical center of the bit. when the proper number of data bits and parity bit (if any) have been assembled, and one/half stop bit has been detected the byte is loaded to the rxfifo. the least significant bit is received first. the data is then transferred to the receive fifo and the rxrdy bit in the sr is set to a 1. this condition can be programmed to generate an interrupt at op4 or op5 and intrn. if the character length is less than 8 bits, the most significant unused bits in the rxfifo are set to zero. after the stop bit is detected, the receiver will immediately look for the next start bit. however if a framing error occurs (a non-zero character was received without a stop bit) and then rxd remains low one/half bit time the receiver operates as if a new start bit was detected. it then continues to assemble the next character. the parity error, framing error, and overrun error (if any) are strobed into the sr from the next byte to be read from the rx fifo. if a break condition is detected (rxd is low for the entire character including the stop bit), a character consisting of all zeros will be loaded into the rxfifo and the received break bit in the sr is set to 1. the rxd input must return to high for two (2) clock edges of the x1 crystal clock for the receiver to recognize the end of the break condition and begin the search for a start bit. this will usually require a high time of one x1 clock period or 3 x1 edges since the clock of the controller is not synchronous to the x1 clock. transmitter reset and disable note the difference between transmitter disable and reset. a transmitter reset stops transmitter action immediately, clears the transmitter fifo and returns the idle state. a transmitter disable withdraws the transmitter interrupts but allows the transmitter to continue operation until all bytes in its fifo and shift register have been transmitted including the final stop bits. it then returns to its idle state. receiver fifo the rxfifo consists of a first-in-first-out (fifo) stack with a capacity of 8 or 16 characters. data is loaded from the receive shift register into the topmost empty position of the fifo. the rxrdy bit
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 19 in the status register is set whenever one or more characters are available to be read, and a ffull status bit is set if all 8 or 16 stack positions are filled with data. either of these bits can be selected to cause an interrupt. a read of the rxfifo outputs the data at the top of the fifo. after the read cycle, the data fifo and its associated status bits (see below) are `popped' thus emptying a fifo position for new data. a disabled receiver with data in its fifo may generate an interrupt (see areceiver status bitso, below). its status bits remain active and its watchdog, if enabled, will continue to operate. receiver status bits in addition to the data word, three status bits (parity error, framing error, and received break) are also appended to the data character in the fifo. the overrun error, mr1[5], and the change of break (isr[2]) are not fifoed. the status of the rx fifo may be provided in two ways, as programmed by the error mode control bit in the mode register (mr1[5]). in the `character' mode, status is provided on a character-by-character basis; the status applies only to the character at the top of the fifo. in the `block' mode, the status provided in the sr for these three bits is the logical-or of the status for all characters coming to the top of the fifo since the last `reset error' from the command register was issued. in either mode reading the sr does not affect the fifo. the fifo is `popped' only when the rxfifo is read. therefore the status register should be read prior to reading the fifo. if the fifo is full when a new character is received, that character is held in the receive shift register until a fifo position is available. if an additional character is received while this state exits, the contents of the fifo are not affected; the character previously in the shift register is lost and the overrun error status bit (sr[4]) will be set-upon receipt of the start bit of the new (overrunning) character. the receiver can control the deactivation of rts. if programmed to operate in this mode, the rtsn output will be negated when a valid start bit was received and the fifo is full. when a fifo position becomes available, the rtsn output will be re-asserted (set low) automatically. this feature can be used to prevent an overrun, in the receiver, by connecting the rtsn output to the ctsn input of the transmitting device. if the receiver is disabled, the fifo characters can be read. however, no additional characters can be received until the receiver is enabled again. if the receiver is reset, the fifo and all of the receiver status, and the corresponding output ports and interrupt are reset. no additional characters can be received until the receiver is enabled again. receiver reset and disable receiver disable stops the receiver immediatelyedata being assembled in the receiver shift register is lost. data and status in the fifo is preserved and may be read. a re-enable of the receiver after a disable will cause the receiver to begin assembling characters at the next start bit detected. a receiver reset will discard the present shift register date, reset the receiver ready bit (rxrdy), clear the status of the byte at the top of the fifo and re-align the fifo read/write pointers. watchdog a `watchdog timer' is associated with the receiver. its interrupt is enabled by mr0[7]. the purpose of this timer is to alert the control processor that characters are in the rxfifo which have not been read. this situation may occur at the end of a transmission when the last few characters received are not sufficient to cause an interrupt. this counter times out after 64 bit times. it is reset each time a character is transferred from the receiver shift register to the rxfifo or a read of the rxfifo is executed. receiver time-out mode in addition to the watch dog timer described in the receiver section, the counter/timer may be used for a similar function. its 16-bit programmability allows much greater precision of time out intervals. the time-out mode uses the received data stream to control the counter. each time a received character is transferred from the shift register to the rxfifo, the counter is restarted. if a new character is not received before the counter reaches zero count, the counter ready bit is set, and an interrupt can be generated. this mode can be used to indicate when data has been left in the rxfifo for more than the programmed time limit. otherwise, if the receiver has been programmed to interrupt the cpu when the receive fifo is full, and the message ends before the fifo is full, the cpu may not know there is data left in the fifo. the ctu and ctl value would be programmed for just over one character time, so that the cpu would be interrupted as soon as it has stopped receiving continuous data. this mode can also be used to indicate when the serial line has been marking for longer than the programmed time limit. in this case, the cpu has read all of the characters from the fifo, but the last character received has started the count. if there is no new data during the programmed time interval, the counter ready bit will get set, and an interrupt can be generated. the time-out mode is enabled by writing the appropriate command to the command register. writing an 0xan to cr will invoke the time-out mode for that channel. writing a `cx' to cr will disable the time-out mode. the time-out mode should only be used by one channel at once, since it uses the c/t. ctu and ctl must be loaded with a value greater than the normal receive character period. the time-out mode disables the regular start/stop counter commands and puts the c/t into counter mode under the control of the received data stream. each time a received character is transferred from the shift register to the rxfifo, the c/t is stopped after 1 c/t clock, reloaded with the value in ctu and ctl and then restarted on the next c/t clock. if the c/t is allowed to end the count before a new character has been received, the counter ready bit, isr[3], will be set. if imr[3] is set, this will generate an interrupt. receiving a character after the c/t has timed out will clear the counter ready bit, isr[3], and the interrupt. invoking the `set time-out mode on' command, crx = `ax', will also clear the counter ready bit and stop the counter until the next character is received. watchdog and time out mode differences the watchdog timer is restarted each time a character is read from or written to the rx fifo. it is an indicator that data is in the fifo that has not been read. if the rx fifo is empty no action occurs. in the time out mode the c/t is stopped and restarted each time a character is written to the rx fifo. from this point of view the time out of the c/t is an indication that the data stream has stopped. after the time out mode is invoked the timer will not start until the first character is written to the rx fifo. time out mode caution when operating in the special time out mode, it is possible to generate what appears to be a afalse interrupto, i.e. an interrupt without a cause. this may result when a time-out interrupt occurs and then, before the interrupt is serviced, another character is received, i.e., the data stream has started again. (the interrupt
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 20 latency is longer than the pause in the data stream.) in this case, when a new character has been received, the counter/timer will be restarted by the receiver, thereby withdrawing its interrupt. if, at this time, the interrupt service begins for the previously seen interrupt, a read of the isr will show the acounter readyo bit not set. if nothing else is interrupting, this read of the isr will return a x'00 character. multi-drop mode (9-bit or wake-up) the uart is equipped with a wake up mode for multi-drop applications. this mode is selected by programming bits mr1[4:3]or to `11'. in this mode of operation, a `master' station transmits an address character followed by data characters for the addressed `slave' station. the slave station(s) whose receiver(s) that are normally disabled, examine the received data stream and `wakeup' the cpu (by setting rxrdy) only upon receipt of an address character. the cpu compares the received address to its station address and enables the receiver if it wishes to receive the subsequent data characters. upon receipt of another address character, the cpu may disable the receiver to initiate the process again. a transmitted character consists of a start bit, the programmed number of data bits, and address/data (a/d) bit, and the programmed number of stop bits. the polarity of the transmitted a/d bit is selected by the cpu by programming bit mr1[2]. mr1[2]= 0 transmits a zero in the a/d bit position, which identifies the corresponding data bits as data. mr1[2] = 1 transmits a one in the a/d bit position, which identifies the corresponding data bits as an address. the cpu should program the mode register prior to loading the corresponding data bits into the txfifo. mr1[2] = 1 transmits a one in the a/d bit position, which identifies the corresponding data bits as an address. the cpu should program the mode register prior to loading the corresponding data bits into the txfifo. in this mode, the receiver continuously looks at the received data stream, whether it is enabled or disabled. if disabled, it sets the rxrdy status bit and loads the character into the rxfifo if the received a/d bit is a one (address tag), but discards the received character if the received a/d bit is a zero (data tag). if enabled, all received characters are transferred to the cpu via the rxfifo. in either case, the data bits are loaded into the data fifo while the a/d bit is loaded into the status fifo position normally used for parity error (sr[5] ). framing error, overrun error, and break detect operate normally whether or not the receiver is enabled. programming the operation of the uart is programmed by writing control words into the appropriate registers. operational feedback is provided via status registers which can be read by the cpu. the addressing of the registers is described in table 1. the contents of certain control registers are initialized to zero on reset. care should be exercised if the contents of a register are changed during operation, since certain changes may cause operational problems. for example, changing the number of bits per character while the transmitter is active may cause the transmission of an incorrect character. in general, the contents of the mr, the csr, and the opcr should only be changed while the receiver(s) and transmitter(s) are not enabled, and certain changes to the acr should only be made while the c/t is stopped. the channel has 3 mode registers (mr0, 1, 2) which control the basic configuration of the channel. access to these registers is controlled by independent mr address pointers. these pointers are set to 0 or 1 by mr control commands in the command register amiscellaneous commandso. each time the mr registers are accessed the mr pointer increments, stopping at mr2. it remains pointing to mr2 until set to 0 or 1 via the miscellaneous commands of the command register. the pointer is set to 1 on reset for compatibility with previous philips semiconductors uart software. refer to table 2 for register bit descriptions. the reserved registers at addresses 0x02 and 0x0a should never be read during normal operation since they are reserved for internal diagnostics. table 1. SC28L91 register addressing address bits a[3:0] read (rdn = 0) write (wrn = 0) 0 0 0 0 mode register(mr0, mr1, mr2) mode register(mr0, mr1, mr2) 0 0 0 1 status register(sr) clock select register(csr) 0 0 1 0 reserved command register(cr) 0 0 1 1 rx holding register(rxfifo) tx holding register(rxfifo) 0 1 0 0 input port change register (ipcr) aux. control register (acr) 0 1 0 1 interrupt status register (isr) interrupt mask register (imr) 0 1 1 0 counter/timer upper (ctu) c/t upper preset register (ctpu) 0 1 1 1 counter/timer lower (ctl) c/t lower preset register (ctpl) 1 1 0 0 interrupt vector (68k mode), misc. register in intel mode interrupt vector (68k mode), misc. register in intel mode 1 1 0 0 ivr motorola mode, misc. register (intel mode) ivr motorola mode, misc. register (intel mode) 1 1 0 1 input port (ipr) output port configuration register (opcr) 1 1 1 0 start counter command set output port bits command (sopr) 1 1 1 1 stop counter command reset output port bits command (ropr) note: 1. the three mr registers are accessed via the mr pointer and commands 0x1n and 0xbn (where n = represents receiver and transmit ter enable bits)
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 21 register acronyms and read / write capability (r/w = read/write, r = read only, w = write only) mode register mrn r/w status register sr r clock select csr w command register cr w receiver fifo rxfifo r transmitter fifo rxfifo w input port change register ipcr r auxiliary control register acr w interrupt status register isr r interrupt mask register imr w counter timer upper value ctu r counter timer lower value ctl r counter timer preset upper ctpu w counter timer preset lower ctpl w input port register ipr r output configuration register opcr w set output port bits w reset output port bits w interrupt vector or gp register ivr/gp r/w table 2. condensed register bit formats n ame adr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mr0 0 watch dog rxint bit 2 txint [1:0] fifo size baud rate extended ii test 2 baud rate extended 1 mr1 0 rxrts control rxint bit 1 error mode parity mode parity type bits per character mr2 0 channel mode txrts con- trol ctsn enable tx stop bit length csr 1 receiver clock, select code transmitter clock select code, sr 1 received break framing er- ror parity error overrun error txemt txrdy rxfull rxrdy cr 2 channel command codes disable tx enable tx disable rx enable rx rxfifo 3 read 8 bits from rx fifo txfifo 3 write 8 bits to tx fifo ipcr 4 delta ip3 delta ip2 delta ip1 delta ip0 state of ip3 state of ip2 state of ip1 state of ip0 acr 4 baud group counter timer mode and clock select enable ip3 enable ip2 enable ip1 enable ip0 isr 5 change in- put port ignore in isr reads counter ready change break rxrdy txrdy imr 5 change in- put port set to 0 set to 0 set to 0 counter ready change break rxrdy txrdy ctu 6 read 8 msb of the brg timer divisor. ctpu 6 write 8 msb of the brg timer divisor. ctl 7 read 8 lsb of the brg timer divisor. ctpl 7 write 8 lsb of the brg timer divisor. ipr d state of ip state of ip 6 state of ip 5 state of ip 4 state of ip 3 state of ip 2 state of ip1 state of ip 0 opcr d configure op7 configure op6 configure op5 configure op4 configure op3 configure op2 strt c/t e read address e to start counter timer sopr e set op 7 set op 6 set op 5 set op 4 set op 3 set op 2 set op 1 set op 0 stp c/t f read address f to stop counter timer ropr f reset op 7 reset op 6 reset op 5 reset op 4 reset op 3 reset op 2 reset op 1 reset op 0
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 22 register descriptions mode registers mr0 mode register 0 mode register 0. mr0 is accessed by setting the mr pointer to 0 via the command register command b. addr bit 7 bit 6 bits 5:4 bit 3 bit 2 bit 1 bit 0 mr0 rx watchdog rxint bit 2 txint (1:0) fifo size baud rate extended ii test 2 baud rate extended 1 0x00 0x08 0 = disable 1 = enable see tables in mr0 descrip- tion see table 4 0 = 8 byte fifo 1 = 16 byte fifo 0 = normal 1 = extend ii set to 0 0 = normal 1 = extend mr0[7]ewatchdog control this bit controls the receiver watchdog timer. 0 = disable, 1 = enable. when enabled, the watch dog timer will generate a receiver interrupt if the receiver fifo has not been accessed within 64 bit times of the receiver 1x clock. this is used to alert the control processor that data is in the rxfifo that has not been read. this situation may occur when the byte count of the last part of a message is not large enough to generate an interrupt. mr0[6]erx interrupt bit 2 bit 2 of receiver fifo interrupt level. this bit along with bit 6 of mr1 sets the fill level of the fifo that generates the receiver interrupt. mr0[6], mr1[6] rx interrupt bits note that this control is split between mr0 and mr1. this is for backward compatibility to legacy software of the sc2692 and scn2681 dual uart devices. table 3. receiver fifo interrupt fill level (mr0(3) = 0 (8 bytes) mr0[6] mr1[6] interrupt condition 00 1 or more bytes in fifo (rx rdy) 01 6 or more bytes in fifo 10 4 or more bytes in fifo 11 8 bytes in fifo (rx full) table 3a. receiver fifo interrupt fill level(mr0(3)=1 (16 bytes) mr0[6] mr1[6] interrupt condition 00 1 or more bytes in fifo (rx rdy) 01 8 or more bytes in fifo 10 12 or more bytes in fifo 11 16 bytes in fifo (rx full) for the receiver these bits control the number of fifo positions filled when the receiver will attempt to interrupt. after the reset the receiver fifo is empty. the default setting of these bits cause the receiver to attempt to interrupt when it has one or more bytes in it. mr0[5:4]etx interrupt fill level. table 4. transmitter fifo interrupt fill level mr0(3) = 0 (8 bytes) mr0[5:4] interrupt condition 00 8 bytes empty (tx empty) 01 4 or more bytes empty 10 6 or more bytes empty 11 1 or more bytes empty (tx rdy) table 4a. transmitter fifo interrupt fill level mr0(3) = 1 (16 bytes) mr0[5:4] interrupt condition 00 16 bytes empty (tx empty) 01 8 or more bytes empty 10 12 or more bytes empty 11 1 or more bytes empty (tx rdy) for the transmitter these bits control the number of fifo positions empty when the transmitter will attempt to interrupt. after the reset the transmit fifo has 8 bytes empty. it will then attempt to interrupt as soon as the transmitter is enabled. the default setting of the mr0 bits [5:4] condition the transmitter to attempt to interrupt only when it is completely empty. as soon as onebyte is loaded, it is no longer empty and hence will withdraw its interrupt request. mr0[3]efifo size selects the fifo depth at 8 or 16 bytes. see tables 3 and 4 mr0[2:0]ebaud rate group selection these bits are used to select one of the sixbaud rate groups. see table 5 for the group organization. ? 000 normal mode ? 001 extended mode i ? 100 extended mode ii other combinations of mr2[2:0] should not be used.
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 23 mr1 mode register 1 addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mr1 rx controls rts rxint bit 1 error mode parity mode parity type bits per character 0x00 0 = no 1 = yes 0 = rxrdy 1 = ffull 0 = char 1 = block 00 = with parity 01 = force parity 10 = no parity 11 = multi-drop mode 0 = even 1 = odd 00 = 5 01 = 6 10 = 7 11 = 8 note: in block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset. mr1 is accessed when the mr pointer points to mr1. the pointer is set to mr1 by reset or by a `set pointer' command applied via cr command 0x10. after reading or writing mr1, the pointer will point to mr2 and will not move from mr2 on subsequent mr reads or writes. mr1[7]e receiver requesttosend control (flow control) this bit controls the deactivation of the rtsn output (op0) by the receiver. this output is normally asserted by setting opr[0] and negated by resetting opr[0]. proper automatic operation of flow control requires opr[0] to be set to logical 1. mr1[7] = 1 causes rtsn to be negated (op0 is driven to a `1' [v cc ]) upon receipt of a valid start bit if the fifo is full. this is the beginning of the reception of the ninth byte. if the fifo is not read before the start of the tenth or 17th byte, an overrun condition will occur and the tenth or 17th or 17th byte will be lost. however, the bit in opr[0] is not reset and rtsn will be asserted again when an empty fifo position is available. this feature can be used for flow control to prevent overrun in the receiver by using the rtsn output signal to control the ctsn input of the transmitting device. mr1[6]erx interrupt bit 1 bit 1 of the receiver interrupt control. see description under mr0[6]. mr1[5]e error mode select this bit selects the operating mode of the three fifoed status bits (fe, pe, and received break) for. in the `character' mode, status is provided on a character-by-character basis; the status applies only to the character at the top of the fifo. in the `block' mode, the status provided in the sr for these bits is the accumulation (logical-or) of the status for all characters coming to the top of the fifo since the last `reset error' command was issued. mr1[4:3|e parity mode select if `with parity' or `force parity' is selected a parity bit is added to the transmitted character and the receiver performs a parity check on incoming data mr1[4:3] = 11 selects operation in the special multidrop mode described in the operation section. mr1[2]e parity type select this bit selects the parity type (odd or even) if the `with parity' mode is programmed by mr1[4:3], and the polarity of the forced parity bit if the `force parity' mode is programmed. it has no effect if the `no parity' mode is programmed. in the special multi-drop mode it selects the polarity of the a/d bit. mr1[1:0]e bits per character select this field selects the number of data bits per character to be transmitted and received. the character length does not include the start, parity, and stop bits.
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 24 mr2 mode register 2 mr2 is accessed when the mr pointer points to mr2, which occurs after any access to mr1. accesses to mr2 do not change the poin ter. addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mr channel mode tx controls rts cts enable tx stop bit length note : add 0.5 to binary codes 07 for 5 bit character lengths. 0x00 00 = normal 0 = 0.563 4 = 0.813 8 = 1.563 c = 1.813 01 = auto-echo 0 = no 0 = no 1 = 0.625 5 = 0.875 9 = 1.625 d = 1.875 10 = local loop 1 = yes 1 = yes 2 = 0.688 6 = 0.938 a = 1.688 e = 1.938 11 = remote loop 3 = 0.750 7 = 1.000 b = 1.750 f = 2.000 note: add 0.5 to values shown for 07 if channel is programmed for 5 bits/char. mr2[7:6]e mode select the channel of the uart can operate in one of four modes. mr2[7:6] = 00 is the normal mode, with the transmitter and receiver operating independently. mr2[7:6] = 01 places the channel in the automatic echo mode, which automatically retransmits the received data. the following conditions are true while in automatic echo mode: 1. received data is reclocked and retransmitted on the txd output. 2. the receive clock is used for the transmitter. 3. the receiver must be enabled, but the transmitter needs not be enabled. 4. the txrdy and txemt status bits are inactive. 5. the received parity is checked, but is not regenerated for transmission, i.e. transmitted parity bit is as received. 6. character framing is checked, but the stop bits are retransmitted as received. 7. a received break is echoed as received until the next valid start bit is detected. 8. cpu to receiver communication continues normally, but the cpu to transmitter link is disabled. mr2[7:6] = 10 selects local loop back diagnostic mode. in this mode: 1. the transmitter output is internally connected to the receiver input. 2. the transmit clock is used for the receiver. 3. the txd output is held high. 4. the rxd input is ignored. 5. the transmitter must be enabled, but the receiver need not be enabled. 6. cpu to transmitter and receiver communications continue normally. mr2[7:6] = 11 selects remote loop back diagnostic mode. in this mode: 1. received data is reclocked and retransmitted on the txd output. 2. the receive clock is used for the transmitter. 3. received data is not sent to the local cpu, and the error status conditions are inactive. 4. the received parity is not checked and is not regenerated for transmission, i.e., transmitted parity is as received. 5. the receiver must be enabled. 6. character framing is not checked, and the stop bits are retransmitted as received. 7. a received break is echoed as received until the next valid start bit is detected. the user must exercise care when switching into and out of the various modes. the selected mode will be activated immediately upon mode selection, even if this occurs in the middle of a received or transmitted character. likewise, if a mode is deselected the device will switch out of the mode immediately. an exception to this occurs when switching out of auto echo or remote loop back modes. if the de-selection occurs just after the receiver has sampled the stop bit (indicated in auto echo by assertion of rxrdy) and the transmitter is enabled, then the transmitter will remain in auto echo mode until the stop bit(s) have been re-transmitted. in most situations the above is rendered transparent by other system considerations. however recall that the stop bit sequence may be very long compared to bus cycles. if rapid reconfiguration of the transmitter is desired in the above conditions the controlling system should wait for the txemt bit to set or issue a tx software reset before reconfiguration begins. mr2[5]e transmitter requesttosend control this bit controls the deactivation of the rtsn output (op0) by the transmitter. this output is normally asserted by setting opr[0] and negated by resetting opr[0]. mr2[5] = 1 caused opr[0] to be reset automatically one bit time after the characters in the transmit shift register and in the txfifo, if any, are completely transmitted including the programmed number of stop bits, if the transmitter is not enabled. this feature can be used to automatically terminate the transmission of a message as follows (aline turnaroundo): 1. program autoreset mode: mr2[5] = 1. 2. enable transmitter. 3. asset rtsn: opr[0] = 1. 4. send message. 5. disable transmitter after the last character is loaded into the txfifo.
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 25 6. the last character will be transmitted and opr[0] will be reset one bit time after the last stop bit, causing rtsn to be negated. mr2[4]e clear-to-send control if this bit is 0, ctsn has no effect on the transmitter. if this bit is a 1, the transmitter checks the state of ctsn (ip0) the time it is ready to send a character. if ip0 is asserted (low), the character is transmitted. if it is negated (high), the txd output remains in the marking state and the transmission is delayed until ctsn goes low. changes in ctsn while a character is being transmitted do not affect the transmission of that character.. mr2[3:0]e stop bit length select this field programs the length of the stop bit appended to the transmitted character. stop bit lengths of 9/16 to 1 and 19/16 to 2 bits, in increments of 1/16 bit, can be programmed for character lengths of 6, 7, and 8 bits. for a character lengths of 5 bits, 11/16 to 2 stop bits can be programmed in increments of 1/16 bit. in all cases, the receiver only checks for a `mark' condition at the center of the stop bit position (one half-bit time after the last data bit, or after the parity bit if enabled is sampled). if an external 1x clock is used for the transmitter, then mr2[3] = 0 selects one stop bit and mr2[3] = 1 selects two stop bits to be transmitted.
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 26 csr clock select register addr csr (7:4) csr (3:0) csr receiver clock select transmitter clock select 0x01 see text and table 5 see text and table 5 table 5. baud rate (base on a 3.6864mhz crystal clock) mr0[0] = 0 (normal mode) mr0[0] = 1 (extended mode i) mr0[2] = 1 (extended mode ii) csra[7:4] acr[7] = 0 acr[7] = 1 acr[7] = 0 acr[7] = 1 acr[7] = 0 acr[7] = 1 0000 50 75 300 450 4,800 7,200 0001 110 110 110 110 880 880 0010 134.5 134.5 134.5 134.5 1,076 1,076 0011 200 150 1200 900 19.2k 14.4k 0100 300 300 1800 1800 28.8k 28.8k 0101 600 600 3600 3600 57.6k 57.6k 0110 1,200 1,200 7200 7,200 115.2k 115.2k 0111 1,050 2,000 1,050 2,000 1,050 2,000 1000 2,400 2,400 14.4k 14.4k 57.6k 57.6k 1001 4,800 4,800 28.8k 28.8k 4,800 4,800 1010 7,200 1,800 7,200 1,800 57.6k 14.4k 1011 9,600 9,600 57.6k 57.6k 9,600 9,600 1100 38.4k 19.2k 230.4k 115.2k 38.4k 19.2k 1101 timer timer timer timer timer timer 1110 ip416x ip416x ip416x ip416x ip416x ip416x 1111 ip41x ip41x ip41x ip41x ip41x ip41x note: 1. the receiver clock is always a 16x clock except for csr[7:4] = 1111. csr[3:0]e transmitter clock select. this field selects t he baud rate clock for the transmitter. the field definition is as shown in table 5, except as follows: csr[3:0] 1110 ip3 16x 1111 ip3 1x the transmitter clock is always a 16x clock except for csr[3:0] = 1111. table 6. bit rate generator characteristics for crystal or clock = 3.6864mhz normal rate (baud) actual 16x clock (khz) error (%) 50 0.8 0 75 1.2 0 110 1.759 0.069 134.5 2.153 0.059 150 2.4 0 200 3.2 0 300 4.8 0 600 9.6 0 1050 16.756 0.260 1200 19.2 0 1800 28.8 0 2000 32.056 0.175 2400 38.4 0 4800 76.8 0 7200 115.2 0 9600 153.6 0 19.2k 307.2 0 38.4k 614.4 0 note: duty cycle of 16x clock is 50% 1%
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 27 crecommand register cr is a register used to supply commands to the uart. multiple commands can be specified in a single write to cr as long as the commands are nonconflicting, e.g., the `enable transmitter' and `reset transmitter' commands cannot be specified in a single command word. cr command register addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cr miscellaneous commands disable tx enable tx disable rx enable rx 0x02 see text of channel command register 1 = yes 0 = no 1 = yes 0 = no 1 = yes 0 = no 1 = yes 0 = no notes: access to the miscellaneous commands should be separated by 3 x1 clock edges. a disabled transmitter cannot be loaded. cr[7:4]emiscellaneous commands execution of the commands in the upper four bits of this register must be separated by 3 x1 clock edges. other reads or writes (including writes to the lower four bits) may be inserted to achieve this separation. cr[7:4]ecommands 0000 no command. 0001 reset mr pointer. causes the mr pointer to point to mr1. 0010 reset receiver. resets the receiver as if a hardware reset had been applied. the receiver is disabled and the fifo is flushed. 0011 reset transmitter. resets the transmitter as if a hard- ware reset had been applied. 0100 reset error status. clears the received break, parity error, and overrun error bits in the status register (sr[7:4]). used in character mode to clear oe status (although received break, pe and fe bits will also be cleared) and in block mode to clear all error status after a block of data has been received. 0101 reset break change interrupt. causes the break detect change bit in the interrupt status register (isr[2]) to be cleared to zero 0110 start break. forces the txd output low (spacing). if the transmitter is empty the start of the break condition will be delayed up to two bit times. if the transmitter is ac- tive the break begins when transmission of the charac- ter is completed. if a character is in the txfifo, the start of the break will be delayed until that character, or any other loaded subsequently are transmitted. the transmitter must be enabled for this command to be accepted. 0111 stop break. the txd line will go high (marking) within two bit times. txd will remain high for one bit time be- fore the next character, if any, is transmitted. 1000 assert rtsn. causes the rtsn output to be asserted (low). 1001 negate rtsn. causes the rtsn output to be negated (high) 1010 set timeout mode on. the receiver in this channel will restart the c/t as the receive character is transferred from the shift register to the rxfifo. the c/t is placed in the counter mode, the start/stop counter com- mands are disabled, the counter is stopped, and the counter ready bit, isr[3], is reset. (see also watch- dog timer description in the receiver section.) 1011 set mr pointer to `0' 1100 disable timeout mode. this command returns control of the c/t to the regular start/stop counter com- mands. it does not stop the counter, or clear any pend- ing interrupts. after disabling the timeout mode, a `stop counter' command should be issued to force a reset of the isr[3] bit 1101 not used. 1110 power down mode on. in this mode, the uart oscilla- tor is stopped and all functions requiring this clock are suspended. the execution of commands other than disable power down mode (1111) requires a x1/clk. while in the power down mode, do not issue any com- mands to the cr except the disable power down mode command. the contents of all registers will be saved while in this mode. it is recommended that the transmit- ter and receiver be disabled prior to placing the uart into power down mode. 1111 disable power down mode. this command restarts the oscillator. after invoking this command, wait for the os- cillator to start up before writing further commands to the cr. cr[3]edisable transmitter this command terminates transmitter operation and reset the txrdy and txemt status bits. however, if a character is being transmitted or if a character is in the txfifo when the transmitter is disabled, the transmission of the character(s) is completed before assuming the inactive state. cr[2]eenable transmitter enables operation of the transmitter. the txrdy and txemt status bits will be asserted if the transmitter is idle. cr[1]edisable receiver this command terminates operation of the receiver immediatelyea character being received will be lost. the command has no effect on the receiver status bits or any other control registers. if the special multi-drop mode is programmed, the receiver operates even if it is disabled. see operation section. cr[0]eenable receiver enables operation of the receiver. if not in the special wakeup mode, this also forces the receiver into the search for startbit state.
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 28 sr status register addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sr received break 1 framing error 1 parity error 1 overrun error txemt txrdy ffull rxrdy 0x01 0 = no 1 = yes 0 = no 1 = yes 0 = no 1 = yes 0 = no 1 = yes 0 = no 1 = yes 0 = no 1 = yes 0 = no 1 = yes 0 = no 1 = yes 1. these status bits are appended to the corresponding data character in the receive fifo. a read of the status provides these b its [7:5] from the top of the fifo together with bits [4:0]. these bits are cleared by a areset error statuso command. in character mode they are discarded when the corresponding data character is read from the fifo. in block error mode, the errorreset command (command 4x or receiv er reset) must used to clear block error conditions. sr[7]e received break this bit indicates that an all zero character of the programmed length has been received without a stop bit. only a single fifo position is occupied when a break is received: further entries to the fifo are inhibited until the rxd line returns to the marking state for at least one-half a bit time two successive edges of the internal or external 1x clock. this will usually require a high time of one x1 clock period or 3 x1 edges since the clock of the controller is not synchronous to the x1 clock . when this bit is set, the `change in break' bit in the isr (isr[2]) is set. isr[2] is also set when the end of the break condition, as defined above, is detected. the break detect circuitry can detect breaks that originate in the middle of a received character. however, if a break begins in the middle of a character, it must persist until at least the end of the next character time in order for it to be detected. this bit is reset by command 4 (0100) written to the command register or by receiver reset. sr[6]e framing error this bit, when set, indicates that a stop bit was not detected (not a logical 1) when the corresponding data character in the fifo was received. the stop bit check is made in the middle of the first stop bit position. sr[5]e parity error this bit is set when the `with parity' or `force parity' mode is programmed and the corresponding character in the fifo was received with incorrect parity. in the special multi-drop mode the parity error bit stores the receive a/d (address/data) bit. sr[4]e overrun error this bit, when set, indicates that one or more characters in the received data stream have been lost. it is set upon receipt of a new character when the fifo is full and a character is already in the receive shift register waiting for an empty fifo position. when this occurs, the character in the receive shift register (and its break detect, parity error and framing error status, if any) is lost. this bit is cleared by a `reset error status' command. sr[3]e transmitter empty (txemt) this bit will be set when the transmitter under runs, i.e., both the txemt and txrdy bits are set. this bit and txrdy are set when the transmitter is first enabled and at any time it is re-enabled after either (a) reset, or (b) the transmitter has assumed the disabled state. it is always set after transmission of the last stop bit of a character if no character is in the thr awaiting transmission. it is reset when the thr is loaded by the cpu, a pending transmitter disable is executed, the transmitter is reset, or the transmitter is disabled while in the under run condition. sr[2]e transmitter ready (txrdy) this bit, when set, indicates that the transmit fifo is not full and ready to be loaded with another character. this bit is cleared when the transmit fifo is loaded by the cpu and there are (after this load) no more empty locations in the fifo. it is set when a character is transferred to the transmit shift register. txrdy is reset when the transmitter is disabled and is set when the transmitter is first enabled. characters loaded to the txfifo while this bit is 0 will be lost. this bit has different meaning from isr[0]. sr[1]e fifo full (ffull) this bit is set when a character is transferred from the receive shift register to the receive fifo and the transfer causes the fifo to become full, i.e., all eight (or 16) fifo positions are occupied. it is reset when the cpu reads the receive fifo. if a character is waiting in the receive shift register because the fifo is full, ffull will not be reset when the cpu reads the receive fifo. this bit has different meaning from irs when mr1 6 is programmed to a `1'. sr[0]e receiver ready (rxrdy) this bit indicates that a character has been received and is waiting in the fifo to be read by the cpu. it is set when the character is transferred from the receive shift register to the fifo and reset when the cpu reads the receive fifo, only if (after this read) there are no more characters in the fifo the rx fifo becomes empty.
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 29 opcr output port configuration register addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 opcr op7 op6 op5 op4 op3 op2 op1 op0 0x0d 0 = opr[7] 0 = opr[6] 0 = opr[5] 0 = opr[4] 00 = opr[3] 00 = opr[2] 1 = reserved 1 = txrdy 1 = reserved 1 = rxrdy/ffull 01 = c/t output 01 = txc(16x) 10 = reserved 10 = txc(1x) 11 = reserved 11 = rxc(1x) opcr[7]eop7 output select this bit programs the op7 output to provide one of the following: 0 the complement of opr[7]. 1 reserved opcr[6]eop6 output select this bit programs the op6 output to provide one of the following: 0 the complement of opr[6]. 1 the transmitter interrupt output which is the complement of isr[0]. when in this mode op6 acts as an open-drain out- put. note that this output is not masked by the contents of the imr. opcr[5]eop5 output select this bit programs the op5 output to provide one of the following: 0 the complement of opr[5]. 1 reserved opcr[4]eop4 output select this field programs the op4 output to provide one of the following: 0 the complement of opr[4]. 1 the receiver interrupt output which is the complement of isr[1]. when in this mode op4 acts as an open-drain out- put. note that this output is not masked by the contents of the imr. opcr[3:2]eop3 output select this bit programs the op3 output to provide one of the following: 00 the complement of opr[3]. 01 the counter/timer output, in which case op3 acts as an open-drain output. in the timer mode, this output is a square wave at the programmed frequency. in the counter mode, the output remains high until terminal count is reached, at which time it goes low. the output returns to the high state when the counter is stopped by a stop counter command. note that this output is not masked by the contents of the imr. 10 reserved 11 reserved opcr[1:0]eop2 output select this field programs the op2 output to provide one of the following: 00 the complement of opr[2]. 01 the 16x clock for the transmitter. this is the clock selected by csr[3:0], and will be a 1x clock if csr[3:0] = 1111. 10 the 1x clock for the transmitter, which is the clock that shifts the transmitted data. if data is not being transmitted, a free running 1x clock is output. 11 the 1x clock for the receiver, which is the clock that samples the received data. if data is not being received, a free run- ning 1x clock is output. sopreset the output port bits (opr) sopr[7:0]eones in the byte written to this register will cause the corresponding bit positions in the opr to set to 1. zeros ha ve no effect. this allows software to set individual bits with our keeping a copy of the opr bit configuration. addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sopr op 7 op 6 op 5 op 4 op 3 op 2 op 1 op 0 0x0e 1 = set bit 1 = set bit 1 = set bit 1 = set bit 1 = set bit 1 = set bit 1 = set bit 1 = set bit 0 = no change 0 = no change 0 = no change 0 = no change 0 = no change 0 = no change 0 = no change 0 = no change roprereset output port bits (opr) ropr[7:0]eones in the byte written to the ropr will cause the corresponding bit positions in the opr to set to 0. zeros have no effect. this allows software to reset individual bits with our keeping a copy of the opr bit configuration. addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ropr op 7 op 6 op 5 op 4 op 3 op 2 op 1 op 0 0x0f 1 = reset bit 1 = reset bit 1 = reset bit 1 = reset bit 1 = reset bit 1 = reset bit 1 = reset bit 1 = reset bit 0 = no change 0 = no change 0 = no change 0 = no change 0 = no change 0 = no change 0 = no change 0 = no change
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 30 opr output port register the output pins (op pins) drive the compliment of the data in this register as controlled by sopr and ropr. addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n/a op 7 op 6 op 5 op 4 op 3 op 2 op 1 op 0 n/a 0 = pin high 0 = pin high 0 = pin high 0 = pin high 0 = pin high 0 = pin high 0 = pin high 0 = pin high 1 = pin low 1 = pin low 1 = pin low 1 = pin low 1 = pin low 1 = pin low 1 = pin low 1 = pin low acr auxiliary control register addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 acr brg set select counter timer mode mode and clock sour select delta ip3 int enable delta ip3 int enable delta ip3 int enable delta ip3 int enable 0x04 0 = set 1 see table 7 0 = off 0 = off 0 = off 0 = off 1 = set 2 1 = enabled 1 = enabled 1 = enabled 1 = enabled acreauxiliary control register acr[7]ebaud rate generator set select this bit selects one of two sets of baud rates to be generated by the brg (see table 5). the selected set of rates is available for use by the receiver and transmitter as described in csr. baud rate generator characteristics are given in table 6. acr[6:4]ecounter/timer mode and clock source select this field selects the operating mode of the counter/timer and its clock source as shown in table 7 acr [3:0]eip3, ip2, ip1, ip0 change-of-state interrupt enable this field selects which bits of the input port change register (ipcr) cause the input change bit in the interrupt status register (isr [7]) to be set. if a bit is in the `on' state the setting of the corresponding bit in the ipcr will also result in the setting of isr [7], which results in the generation of an interrupt output if imr [7] = 1. if a bit is in the `off' state, the setting of that bit in the ipcr has no effect on isr [7]. table 7. acr 6:4 field definition acr 6:4 mode clock source 000 counter external (ip2) 001 counter txc 1x clock of transmitter 010 reserved 011 counter crystal or x1/clk clock divided by 16 100 timer external (ip2) 101 timer external (ip2) divided by 16 110 timer crystal or external clock (x1/clk) 111 timer crystal or external clock (x1/clk) divided by 16 note: 1. the timer mode generates a square wave ipcr input port change register addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ipcr delta ip3 delta ip3 delta ip3 delta ip3 ip 3 ip 2 ip 1 ip 0 0x04 0 = no change 0 = no change 0 = no change 0 = no change 0 = low 0 = low 0 = low 0 = low 1 = change 1 = change 1 = change 1 = change 1 = high 1 = high 1 = high 1 = high ipcr [7:4]eip3, ip2, ip1, ip0 change-of-state these bits are set when a change-of-state, as defined in the input port section of this data sheet, occurs at the respective input pins. they are cleared when the ipcr is read by the cpu. a read of the ipcr also clears isr [7], the input change bit in the interrupt status register. the setting of these bits can be programmed to generate an interrupt to the cpu. ipcr [3:0]eip3, ip2, ip1, ip0 change-of-state these bits provide the current state of the respective inputs. the information is unlatched and reflects the state of the input pins at the time the ipcr is read.
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 31 isreinterrupt status register this register provides the status of all potential interrupt sources. the contents of this register are masked by the interrupt mask register (imr). if a bit in the isr is a `1' and the corresponding bit in the imr is also a `1', the intrn output will be asserted (low). if the corresponding bit in the imr is a zero, the state of the bit in the isr has no effect on the intrn output. note that the imr does not mask the reading of the isr the true status will be provided regardless of the contents of the imr. the contents of this register are initialized to 0x00' when the uart is reset. isr interrupt status register addr bit 7 bits[6:4] bit 3 bit 2 bit 1 bit 0 isr input port change ignore in isr reads. reserved for future function counter ready delta break rxrdy/ ffull txrdy 0x05 0 = not active 0 = not active 0 = not active 0 = not active 0 = not active 1 = active 1 = active 1 = active 1 = active 1 = active isr[7]einput port change status this bit is a `1' when a changeofstate has occurred at the ip0, ip1, ip2, or ip3 inputs and that event has been selected to cause an interrupt by the programming of acr[3:0]. the bit is cleared when the cpu reads the ipcr. isr[6:4]enot used, ignore in isr read. isr[3]ecounter ready. in the counter mode, this bit is set when the counter reaches terminal count and is reset when the counter is stopped by a stop counter command. in the timer mode, this bit is set once the cycle of the generated square wave (every other time that the counter/timer reaches zero count). the bit is reset by a stop counter command. the command, however, does not stop the counter/timer. isr[2]e change in break this bit, when set, indicates that the receiver has detected the beginning or the end of a received break. it is reset when the cpu issues a `reset break change interrupt' command. isr[1]erx interrupt this bit indicates that the receiver is interrupting according to the fill level programmed by the mr0 and mr1 registers. this bit has a different meaning than the receiver ready/full bit in the status register. isr[0]etx interrupt this bit indicates that the transmitter is interrupting according to the interrupt level programmed in the mr0[5:4] bits. this bit has a different meaning than the txrdy bit in the status register. imreinterrupt mask register the programming of this register selects which bits in the isr causes an interrupt output. if a bit in the isr is a `1' and the corresponding bit in the imr is also a `1' the intrn output will be asserted. if the corresponding bit in the imr is a zero, the state of the bit in the isr has no effect on the intrn output. note that the imr does not mask the programmable interrupt outputs op3op7 or the reading of the isr. imr interrupt mask register addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 imr input port change reserved reserved reserved counter ready delta break rxrdy/ ffull txrdy 0x05 0 = not en- abled set to 0 set to 0 set to 0 0 = not en- abled 0 = not en- abled 0 = not en- abled 0 = not en- abled 1 = enabled 1 = enabled 1 = enabled 1 = enabled 1 = enabled ivr/gp interrupt vector register (68k mode) or generalpurpose register (80xxx mode) ivr/gp bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x0c interrupt vector register (68xxx mode) or generalpurpose register (80xxx mode) this register stores the interrupt vector. it is initialized to 0x0f on hardware reset and is usually changed from this value during initialization of the SC28L91 for the 68k mode. the contents of this register will be placed on the data bus when iackn is asserted low or a read of address 0xc is performed. when not operating in the 68xxx mode, this register may be used as a general-purpose one-byte storage register. a convenient use may the storing a ashadowo of the contents of another SC28L91 register (imr, for example).
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 32 ctpu and ctpl counter/timer registers ctpu counter timer preset upper ctpu bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x06 the lower eight (8) bits for the 16 bit counter timer preset register ctpl counter timer preset low ctpl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x07 the upper eight (8) bits for the 16 bit counter timer preset register the ctpu and ctpl hold the eight msbs and eight labs, respectively, of the value to be used by the counter/timer in either the counter or timer modes of operation. the minimum value which may be loaded into the ctpu/ctpl registers is h`0002'. note that these registers are write-only and cannot be read by the cpu. in the timer mode, the c/t generates a square wave whose period is twice the value (in c/t clock periods) of the ctpu and ctpl. the waveform so generated is often used for a data clock. the formula for calculating the divisor n to load to the ctpu and ctpl for a particular 1x data clock is shown below. n = (c/t clock frequency) divided by (2 x 16 x baud rate desired) often this division will result in a non-integer number; 26.3, for example. one can only program integer numbers in a digital divider. therefore 26 would be chosen. this gives a baud rate error of 0.3/26.3 which is 1.14%; well within the ability asynchronous mode of operation. the c/t will not be running until it receives an initial `start counter' command (read at address a3a0 = 1110). after this, while in timer mode, the c/t will run continuously. receipt of a start counter command (read with a3a0 = 1110) causes the counter to terminate the current timing cycle and to begin a new cycle using the values in ctpu and ctpl. if the value in ctpu and ctpl is changed, the current half-period will not be affected, but subsequent half periods will be affected. the counter ready status bit (isr[3]) is set once each cycle of the square wave. the bit is reset by a stop counter command (read with a3a0 = 0xf). the command however, does not stop the c/t. the generated square wave is output on op3 if it is programmed to be the c/t output. in the counter mode, the value c/t loaded into ctpu and ctpl by the cpu is counted down to 0. counting begins upon receipt of a start counter command. upon reaching terminal count 0x0000, the counter ready interrupt bit (isr[3]) is set. the counter continues counting past the terminal count until stopped by the cpu. if op3 is programmed to be the output of the c/t, the output remains high until terminal count is reached, at which time it goes low. the output returns to the high state and isr[3] is cleared when the counter is stopped by a stop counter command. the cpu may change the values of ctpu and ctpl at any time, but the new count becomes effective only on the next start counter commands. if new values have not been loaded, the previous count values are preserved and used for the next count cycle. in the counter mode, the current value of the upper and lower 8 bits of the counter (ctu, ctl) may be read by the cpu. it is recommended that the counter be stopped when reading to prevent potential problems which may occur if a carry from the lower 8 bits to the upper 8 bits occurs between the times that both halves of the counter are read. however, note that a subsequent start counter command will cause the counter to begin a new count cycle using the values in ctpu and ctpl. when the c/t clock divided by 16 is selected, the maximum divisor becomes 1,048,575. output port notes the output ports are controlled from four places: the opcr register, the opr register, the mr registers and the command register (except the 2681 and 68681) the opcr register controls the source of the data for the output ports op2 through op7. the data source for output ports op0 and op1 is controlled by the mr and cr registers. when the opr is the source of the data for the output ports, the data at the ports is inverted from that in the opr register. the content of the opr register is controlled by the aset output port bits commando and the areset output bits commando. these commands are at e and f, respectively. when these commands are used, action takes place only at the bit locations where ones exist. for example, a one in bit location 5 of the data word used with the aset output port bitso command will result in opr[5] being set to one. the op5 would then be set to zero (v ss ). similarly, a one in bit position 5 of the data word associated with the areset output ports bitso command would set opr[5] to zero and, hence, the pin op5 to a one (v dd ). the cts, rts, cts enable tx signals cts (clear to send) is usually meant to be a signal to the transmitter meaning that it may transmit data to the receiver. the cts input is on pin ip0 for tx. the cts signal is active low; thus, it is called ctsn for txrts is usually meant to be a signal from the receiver indicating that the receiver is ready to receive data. it is also active low and is, thus, called rtsn for rx. rtsn is on pin op0. a receiver's rts output will usually be connected to the cts input of the associated transmitter. therefore, one could say that rts and cts are different ends of the same wire! mr2[4] is the bit that allows the transmitter to be controlled by the cts pin (ip0 or ip1). when this bit is set to one and the cts input is driven high, the transmitter will stop sending data at the end of the present character being serialized. it is usually the rts output of the receiver that will be connected to the transmitter's cts input. the receiver will set rts high when the receiver fifo is full and the start bit of the ninth or 17th character is sensed. transmission then stops with nine or 17 valid characters in the receiver. when mr2[4] is set to one, ctsn must be at zero for the transmitter to operate. if mr2[4] is set to zero, the ip pin will have no effect on the operation of the transmitter. mr1[7] is the bit that allows the receiver to control op0. when op0 (or op1) is controlled by the receiver, the meaning of that pin will be.
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 33 resetn t res sd00696 resetn t res 80xxx mode 68xxx mode figure 4. reset timing a0a3 cen t as t cs t ch rdn t rw t rwd d0d7 (read) t dd t df float float valid not valid wdn t rwd valid d0d7 (write) t ds t dh t ah sd00087 note: bus action in the 80xxx mode terminates on the rise of cen, wrn, or rdn which ever one occurs first. figure 5. bus timing (80xxx mode)
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 34 x1/clk a1a4 rwn csn d0d7 dtackn t csc t as t cs t df t dat t dah t ch t rwd t dd t dcr t ah data valid not valid t da note: dackn low requires two rising edges of x1 clock after csn is low. sd00687 figure 6. bus timing (read cycle) (68xxx mode) x1/clk a1a4 rwn csn d0d7 dtackn t csc t as t cs t dh t dat t dah t ch t rwd t ds t dcw t ah note: dackn low requires two rising edges of x1 clock after csn is low. sd00688 figure 7. bus timing (write cycle) (68xxx mode) note: for figures 6 and 7 wrn changing within the time of cen low may cause short read or write pulses that could upset internal poin ters and registers. bus action terminates on the rise of cen or the fall of dackn, which ever occurs first.
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 35 x1/clk intrn iackn d0d7 dtackn t csc t dd t df t csd t dal t dcr t dah t dat note: dackn low requires two rising edges of x1 clock after csn is low. sd00149 figure 8. interrupt cycle timing (68xxx mode) (b) output pins rdn ip0ip6 wrn op0op7 t ps t ph t pd old data new data (a) input pins sd00135 figure 9. port timing
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 36 notes: 1. intrn or op3-op7 when used as interrupt outputs. 2. the test for open-drain outputs is intended to guarantee switching of the output transistor. measurement of this response is referenced from the midpoint of the switching signal, v m , to a point 0.5v above v ol . this point represents noise margin that assures true switching has occurred. beyond this level, the effects of external cir cuitry and test environment are pronounced and can greatly affect the resultant measurement. v m v ol +0.5v v ol wrn interrupt 1 output t ir v m v ol +0.5v v ol rdn interrupt 1 output t ir sd00136 figure 10. interrupt timing (80xxx mode) c1 = c2 ~ 24pf for c l = 20pf t clk t ctc t rx t tx x1/clk ctclk rxc txc t clk t ctc t rx t tx v cc 470 w x1 x2* clk *note: x2 must be left open. x2 3.6864mhz x1 c1 c2 SC28L91 note: resistor required for ttl input. to uart circuit 50k w to 100k w 3pf 3pf c1 and c2 should be chosen according to the crystal manufacturer's specification. c1 and c2 values will include any parasitic capacitance of the wiring and x1 x2 pins. gain at 3.6864mhz: 9 to 13 db 2pf 4pf package capacitance approximately 4pf. sd00704 parasitic capacitance parasitic capacitance figure 11. clock timing
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 37 t txd t tcs 1 bit time (1 or 16 clocks) txd txc (input) txc (1x output) sd00138 figure 12. transmitter external clocks t rxs t rxh rxc (1x input) rxd sd00139 figure 13. receiver external clock transmitter enabled txd d1 d2 d3 d4 d6 break txrdy (sr2) wrn d1 d8 d9 d10 d12 start break stop break d11 will not be written to the txfifo ctsn 1 (ip0) rtsn 2 (op0) opr(0) = 1 opr(0) = 1 notes: 1. timing shown for mr2(4) = 1. 2. timing shown for mr2(5) = 1. sd00155 figure 14. transmitter timing
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 38 d1 d2 d8 d9 d10 d11 d12 d13 rxd d12, d13 will be lost due to receiver disable. receiver enabled rxrdy (sr0) ffull (sr1) rxrdy/ ffull (op5) 2 rdn status data d1 status data d2 status data d3 status data d10 d11 will be lost due to overrun overrun (sr4) reset by command rts 1 (op0) opr(0) = 1 notes: 1. timing shown for mr1(7) = 1. 2. shown for opcr(4) = 1 and mr(6) = 0. sd00156 figure 15. receiver timing transmitter enabled txd add#1 txrdy (sr2) wrn mr1(43) = 11 mr1(2) = 1 1 bit 9 d0 0 bit 9 add#2 1 bit 9 master station add#1 mr1(2) = 0 d0 mr1(2) = 1 add#2 rxd add#1 1 bit 9 d0 0 bit 9 add#2 1 bit 9 peripheral station 0 bit 9 0 bit 9 receiver enabled rxrdy (sr0) rdn/wrn mr1(43) = 11 add#1 status data d0 status data add#2 sd00096 figure 16. wake-up mode
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 39 intrn dackn d0d7 txda/b op0op7 125pf +5v i = 2.4ma 125pf i = 2.4ma v ol return to v cc for a 0 level i = 400 m a v oh return to v ss for a 1 level sd00690 figure 17. test conditions on outputs
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 40 plcc44: plastic leaded chip carrier; 44 leads sot187-2
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 41 qfp44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm sot307-2
philips semiconductors product specification SC28L91 3.3v5.0v universal asynchronous receiver/transmitter (uart) 2000 sep 22 42 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 2000 all rights reserved. printed in u.s.a. date of release: 09-00 document order number: 9397 750 07549

data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

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